HW-V5-ML555-G【PDF 73/108 页】BOARD EVAL FOR VIRTEX-5 ML555

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R

3.

User LEDs

Using one of the clock synthesizer chips. If using the parallel input mode, SW9 and/or

SW11 must be pressed and released to obtain a known output frequency from the

clock synthesizers after a power-on cycle.

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Typically, CLOCK_SYNTH1 is reserved for the DDR2 memory clock generation.

If the DDR2 memory is not used or the clock frequency for the DDR2 memory is

200 MHz, this clock can be used for 200 MHz clock generation. The ML555 board

supports DDR2-400, DDR2-533, and DDR2-667 rates.

CLOCK_SYNTH2 routed through the U3 clock mux goes to GCLK_P J20 and

GCLK_N J21. The SATA_MGT_CLKSEL output port on FPGA pin H15 must be

set to either a logic 1 level to select the Clock Synthesizer 2 as the clock source or a

logic 0 level to select the fixed 125 MHz LVDS clock source as input to the global

clock pins. Depending on which GTP elements are used in the design, the second

clock synthesizer might be available for IDELAYCTRL reference clock.

User LEDs

The ML555 board provides three user LEDs that can be turned ON by driving the LED

signals to Ground. Table 3-27 lists the FPGA pin assignments.

Table 3-27:

User LED Pin Assignments

LED Signal

USER_LED0

USER_LED1

USER_LED2

Designation

USER1 D1

USER2 D2

USER3 D3

FPGA Pin Number (1)

(FF1136 Package)

H8

G8

G10

Notes:

1. These signals are connected to FPGA bank 20. The FPGA reference voltage, V CCO , for this bank is 2.5V.

See the ML555 board schematic on the CD-ROM for additional information.

Configuration INIT and DONE LEDs

The ML555 board provides INIT and DONE indicator LEDs, that are turned ON by the

FPGA during the configuration process. The FPGA INIT pin (N14) drives the INIT LED

(D5) buffer transistor (Q2). The FPGA DONE pin (M15) drives the DONE LED (D6) buffer

transistor (Q1). Table 3-28 lists the FPGA pin assignments.

Table 3-28:

Configuration INIT and DONE LED Pin Assignments

LED

FPGA_INIT

FPGA_DONE

Designation

D5 INIT

D6 DONE

FPGA Pin Number (1)

(FF1136 Package)

N14

M15

Notes:

1. These signals are connected to FPGA configuration bank 0. The FPGA reference voltage for this bank

is 2.5V. See the ML555 board schematics on the CD-ROM for additional information.

Virtex-5 FPGA ML555 Development Kit

UG201 (v1.4) March 10, 2008

73

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